1. Technical Field
The present invention relates to memory circuits and more particularly to a memory circuit and method having/using a level shifter for controlling cell voltages during memory operations.
2. Description of the Related Art
Static Random Access Memory (SRAM) is one of the key components in semiconductor processors and computer systems. As technology advances and printed features in semiconductor chips become smaller, SRAM design is facing a difficult problem which arises from the statistical variation of process parameters in each SRAM cell. Traditionally, SRAM design depends on the symmetric nature of an SRAM cell. When the symmetry is broken due to local variation of process parameters, SRAM designs become susceptible to stability issues where an SRAM cell is so unbalanced and, as a result, it is no longer correctly functional for either read or write operations.
Another challenge in SRAM design is keeping up with ever increasing operating frequency. As technology advances, the devices in an SRAM cell become smaller than those in previous technologies. Since the newer process technologies face tougher problems, device performance may no longer scale at a same rate as feature scaling. As a result, the SRAM cell current in a newer process technology tends to be weaker than previous technologies. This means that SRAM performance may not fare as well compared with the previous technologies.
One of the techniques employed is separating power supplies to SRAM arrays and possibly SRAM array peripherals and boosting one power supply to a higher value than the rest of chip. In this way, the SRAM stability issue decreases, and the SRAM design can gain speed at the same time. However, issues with introducing separate power supplies with different potentials arise. When the difference in potential is small enough, the issue may be negligible. However, when the potential difference becomes large enough, the circuit at the boundary of the two supplies may malfunction or may experience issues such as excessive leakage.